1. Field of the Invention
The invention relates in general to a method of forming a multilevel interconnect in an integrated circuit, and more particularly, to a dual damascene technique.
2. Description of the Related Art
An integrated circuit typically comprises various devices and components. These devices or components are typically insulated by an isolation structure. To electrically connect certain parts of the devices or components, an interconnect is commonly used. In the conventional method of manufacturing interconnects, a conductive layer is deposited over a substrate. A portion of the conductive layer is etched away to form a desired wiring pattern. The wiring pattern is then covered by an insulation layer to avoid any unwanted connected to other conductive layers, components, or devices. A vertical via hole is formed through the insulation layer to electrically connect the wiring layer. In general, an inter-metal dielectric (IMD) layer is used as an insulation layer to isolate the conductive layer from other conductive layer or wiring pattern. The connection between the conductive layer and other conductive layer or wiring pattern is achieved through a vertical via.
At present, two methods of fabricating interconnects such as plugs or vias are used in the semiconductor industry. The first method uses two separate stages for forming the interconnects. A dielectric layer is formed over a first conductive layer, and a photoresist layer is deposited over the dielectric layer. Etching techniques are used to form a via hole, and a conductive material is deposited into the via hole to form a via for electrical connection. A second conductive layer is deposited over the dielectric layer followed by a patterning process.
The second method is a dual damascene process. In the conventional dual damascene process, an insulation layer is first formed over a substrate structure followed by a planarizing process. According to the required wiring pattern and positions of vias, the insulating layer is etched to form horizontal trenches and vertical via holes. In other words, the lower portion of the insulating layer is etched to expose some of the device regions or portions of the metal lines below, thereby to form a vertical via hole. The upper portion of the insulating layer is also etched to form a horizontal trench. A conductive material is then deposited over the substrate structure to fill the horizontal trench and the via hole at the same. Chemical-mechanical polishing (CMP) method is used to planarize the surfaces of the devices, and then another dual damascene process can be carried out again. Since two metal-filling operations for filling the respective horizontal trenches and vertical via holes are combined into a single operation, the operation is referred to as a dual damascene process. Typically, the via is an interconnect between the underlying conductive region and the wiring pattern formed by filling conductive material into the horizontal trench.
FIG. 1A to FIG. 1G shows a conventional dual damascene process. In FIG. 1A, a substrate 100 comprising a conductive region 102 is provided. A silicon oxide layer 104 and a silicon nitride layer 106 are formed on the substrate 100. The silicon nitride layer 106 is functioned as a etch stop in the subsequent etching process. A photo-resist layer 108 is formed to expose a part of the silicon nitride layer 106 aligned over the conductive region 102. The exposed silicon nitride layer 106 is removed to form an opening 107 to expose a part of the silicon oxide layer 104 aligned over the conductive region 102. Being etched, the resultant silicon nitride layer is denoted as 106a.
In FIG. 1C, another silicon oxide layer 114 is formed by chemical vapor deposition (CVD) to cover the silicon nitride layer 106a and the silicon oxide layer 104.
In FIG. 1D, another photo-resist layer with a pattern 118 is formed over the silicon oxide layer 114. The photo-resist layer 118 has openings which expose part of the silicon oxide layer 114. The exposed parts of the silicon oxide layer 114 comprise the region aligned over the conductive region 102 of the substrate and another part for forming an interconnect trench.
In FIG. 1E, using dry etch with a high etching selectivity for silicon oxide against silicon nitride (SiO.sub.2 /SiN), the exposed parts silicon oxide layer 114 are removed to form trenches 120a and 122. The silicon oxide layer 104 exposed within the trench 120a is removed by dry etch with the same etching condition until the conductive region 102 is exposed, so that a via hole 120b is formed. Being etched, the resultant silicon oxide layer are denoted as 114a and 104a. The trench 120a and the via hole 120b are combined to form a dual damascene structured openings as 120.
In FIG. 1F, the photo-resist layer 118 is removed. A conformal glue/barrier layer is formed on each of the surfaces of the opening 120 and the trench 122. The opening 120 and the trench 122 are then filled with conductive layer 126 and 128 respectively to complete the dual damascene process.
While defining the opening 120, the profile thereof is determined by the pattern of the photo-resist layer 118 and the patterned silicon nitride layer 106a. In case of a misalignment as shown in FIG. 1G, the silicon oxide layer 114 exposed by the opening within the photo-resist is not aligned over the conductive region 102 precisely. As a consequence, the opening 120' formed by the trench 120a' and the via hole 120b' (shown in FIG. 1H) only exposes a part of the conductive region 102, so that the contact area of the interconnect 126' formed subsequently is reduced. The reduced contact area increases the contact resistance, and in contrast, reduces the conductivity of the interconnect 126'.
In addition to the above mentioned problem caused by misalignment, a higher fabricating cost is required for the conventional dual damascene process since two inter-metal layers (IMD), that is, two silicon oxide layers in this prior art technique and one silicon nitride layer for etch stop are required.
The silicon nitride layer has a dielectric constant higher than silicon oxide layer, therefore, a parasitic capacitor is easily induced. The internal stress of the silicon nitride layer is different from it of the silicon oxide layer. Moreover, the stress of the silicon nitride is tensile, while the stress of the silicon oxide is compressive. In the subsequent thermal process for metallization, a crack or a peeling effect at the side wall corner of the interface between the silicon nitride layer and the silicon oxide layer is easily caused. The quality of the device is thus degraded.